HD64F3048VTF8 Datasheet, PDF (183/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 6 Bus Controller
Figure 6.19 shows the timing when the bus right is requested by an external bus master during a
read cycle in a two-state-access area. There is a minimum interval of two states from when the
BREQ signal goes low until the bus is released.
φ
Address
bus
CS_n
Data bus
AS , RD High
HWR , LWR
CPU cycles
T₁
T₂
Address
External bus released
High-impedance
High level
High-impedance
High-impedance
High-impedance
CPU cycles
BREQ
BACK
Minimum 2 cycles
1
2
3
4
5
6
1 Low BREQ signal is sampled at rise of T₁ state.
2 BACK signal goes low at end of CPU read cycle, releasing bus right to external bus master.
3 BREQ pin continues to be sampled while bus is released to external bus master.
4, 5 High BREQ signal is sampled twice consecutively.
6 BACK signal goes high, ending bus-release cycle.
Note: n = 7 to 0
Figure 6.19 External-Bus-Released State (Two-State-Access Area, During Read Cycle)
Rev. 3.00 Sep 27, 2006 page 155 of 872
REJ09B0325-0300