HD64F3048VTF8 Datasheet, PDF (805/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

MSTCR—Module Standby Control Register
Appendix B Internal I/O Register
H'5E
System control
Bit
Initial value
Read/Write
7
PSTOP
0
R/W
6
5
4
3
2
1
0
 MSTOP5 MSTOP4 MSTOP3 MSTOP2 MSTOP1 MSTOP0
1
0
0
0
0
0
0

R/W
R/W
R/W
R/W
R/W
R/W
Module standby 0
0 A/D converter operates normally
(Initial value)
1 A/D converter is in standby state
Module standby 1
0 Refresh controller operates normally (Initial value)
1 Refresh controller is in standby state
Module standby 2
0 DMAC operates normally (Initial value)
1 DMAC is in standby state
Module standby 3
0 SCI1 operates normally (Initial value)
1 SCI1 is in standby state
Module standby 4
0 SCI0 operates normally (Initial value)
1 SCI0 is in standby state
Module standby 5
0 ITU operates normally (Initial value)
1 ITU is in standby state
φ clock stop
0 φ clock output is enabled (Initial value)
1 φ clock output is disabled
Rev. 3.00 Sep 27, 2006 page 777 of 872
REJ09B0325-0300