HD64F3048VTF8 Datasheet, PDF (202/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 7 Refresh Controller
2CAS and 2WE Modes
The CAS/WE bit in RFSHCR can select two control modes for 16-bit-wide DRAM: one using
UCAS and LCAS; the other using UW and LW. These DRAM pins correspond to H8/3048B
Group pins as shown in table 7.6.
Table 7.6 DRAM Pins and H8/3048B Group Pins
H8/3048B Group Pin
HWR
LWR
RD
CS
3
CAS/WE = 0 (2WE Mode)
UW
LW
CAS
RAS
DRAM Pin
CAS/WE = 1 (2CAS Mode)
UCAS
LCAS
WE
RAS
Figure 7.5 (1) shows the interface timing for 2WE DRAM. Figure 7.5 (2) shows the interface
timing for 2CAS DRAM.
Read cycle
Write cycle*
Refresh cycle
φ
Address
bus
CS ₃
(RAS)
RD
(CAS)
HWR
(UW)
LWR
(LW)
RFSH
AS
Row
Column
Row
Column
Area 3 top address
Note: * 16-bit access
Figure 7.5(1) DRAM Control Signal Output Timing (2WE Mode)
Rev. 3.00 Sep 27, 2006 page 174 of 872
REJ09B0325-0300