HD64F3048VTF8 Datasheet, PDF (385/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

10.4 Operation
Section 10 16-Bit Integrated Timer Unit (ITU)
10.4.1 Overview
A summary of operations in the various modes is given below.
Normal Operation
Each channel has a timer counter and general registers. The timer counter counts up, and can
operate as a free-running counter, periodic counter, or external event counter. General registers A
and B can be used for input capture or output compare.
Synchronous Operation
The timer counters in designated channels are preset synchronously. Data written to the timer
counter in any one of these channels is simultaneously written to the timer counters in the other
channels as well. The timer counters can also be cleared synchronously if so designated by the
CCLR1 and CCLR0 bits in the TCRs.
PWM Mode
A PWM waveform is output from the TIOCA pin. The output goes to 1 at compare match A and
to 0 at compare match B. The duty cycle can be varied from 0% to 100% depending on the
settings of GRA and GRB. When a channel is set to PWM mode, its GRA and GRB automatically
become output compare registers.
Reset-Synchronized PWM Mode
Channels 3 and 4 are paired for three-phase PWM output with complementary waveforms. (The
three phases are related by having a common transition point.) When reset-synchronized PWM
mode is selected GRA3, GRB3, GRA4, and GRB4 automatically function as output compare
registers, TIOCA₃, TIOCB₃, TIOCA₄, TOCXA₄, TIOCB₄, and TOCXB₄ function as PWM output
pins, and TCNT3 operates as an up-counter. TCNT4 operates independently, and is not compared
with GRA4 or GRB4.
Rev. 3.00 Sep 27, 2006 page 357 of 872
REJ09B0325-0300