HD64F3048VTF8 Datasheet, PDF (199/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 7 Refresh Controller
7.3.2 DRAM Refresh Control
Refresh Request Interval and Refresh Cycle Execution
The refresh request interval is determined by the settings of RTCOR and bits CKS2 to CKS0 in
RTMCSR. Figure 7.2 illustrates the refresh request interval.
RTCOR
RTCNT
H'00
Refresh request
Figure 7.2 Refresh Request Interval (RCYCE = 1)
Refresh requests are generated at regular intervals as shown in figure 7.2, but the refresh cycle is
not actually executed until the refresh controller gets the bus right.
Table 7.4 summarizes the relationship among area 3 settings, DRAM read/write cycles, and
refresh cycles.
Table 7.4 Area 3 Settings, DRAM Access Cycles, and Refresh Cycles
Area 3 Settings
2-state-access area
(AST3 = 0)
3-state-access area
(AST3 = 1)
Read/Write Cycle by CPU
or DMAC
• 3 states
• Wait states cannot be inserted
• 3 states
• Wait states can be inserted
Refresh Cycle
• 3 states
• Wait states cannot be inserted
• 3 states
• Wait states can be inserted
To insert refresh cycles, set the RCYCE bit to 1 in RFSHCR. Figure 7.3 shows the state transitions
for execution of refresh cycles.
When the first refresh request occurs after exit from the reset state or standby mode, the refresh
controller does not execute a refresh cycle, but goes into the refresh request pending state. Note
this point when using a DRAM that requires a refresh cycle for initialization.
Rev. 3.00 Sep 27, 2006 page 171 of 872
REJ09B0325-0300