HD64F3048VTF8 Datasheet, PDF (93/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 2 CPU
is cleared to 0, the CPU sets both the I bit and the UI bit in the condition code register to 1. Then
the CPU fetches a start address from the exception vector table and execution branches to that
address.
Figure 2.14 shows the stack after the exception-handling sequence.
SP − 4
SP − 3
SP − 2
SP − 1
SP (ER7)
Stack area
SP (ER7)
SP + 1
SP + 2
SP + 3
SP + 4
CCR
PC
Even
address
Before exception
handling starts
Legend:
CCR: Condition code register
SP: Stack pointer
Pushed on stack
After exception
handling ends
Notes: 1. PC is the address of the first instruction executed after the return from the
exception-handling routine.
2. Registers must be saved and restored by word access or longword access,
starting at an even address.
Figure 2.14 Stack Structure after Exception Handling
2.8.5 Bus-Released State
In this state the bus is released to a bus master other than the CPU, in response to a bus request.
The bus masters other than the CPU are the DMA controller, the refresh controller, and an external
bus master. While the bus is released, the CPU halts except for internal operations. Interrupt
requests are not accepted. For details see section 6.3.7, Bus Arbiter Operation.
Rev. 3.00 Sep 27, 2006 page 65 of 872
REJ09B0325-0300