HD64F3048VTF8 Datasheet, PDF (729/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

21.3.4 Clock Timing
Clock timing is shown as follows:
• Oscillator settling timing
Figure 21.22 shows the oscillator settling timing.
Section 21 Electrical Characteristics
φ
V_CC
STBY
RES
t_OSC1
Figure 21.22 Oscillator Settling Timing
t_OSC1
21.3.5 TPC and I/O Port Timing
Figure 21.23 shows the TPC and I/O port timing.
φ
Port 1 to B
(read)
Port 1 to 6,
8 to B
(write)
T₁
T₂
T₃
t_PRS
t_PRH
t_PWD
Figure 21.23 TPC and I/O Port Input/Output Timing
Rev. 3.00 Sep 27, 2006 page 701 of 872
REJ09B0325-0300