HD64F3048VTF8 Datasheet, PDF (373/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 10 16-Bit Integrated Timer Unit (ITU)
the general register functions as an input capture register, the buffer register functions as an input
capture buffer register.
The buffer registers are linked to the CPU by an internal 16-bit bus and can be written or read by
either word or byte access.
Buffer registers are initialized to H'FFFF by a reset and in standby mode.
10.2.10 Timer Control Registers (TCR)
TCR is an 8-bit register. The ITU has five TCRs, one in each channel.
Channel
0
1
2
3
4
Abbreviation
TCR0
TCR1
TCR2
TCR3
TCR4
Function
TCR controls the timer counter. The TCRs in all channels are
functionally identical. When phase counting mode is selected in
channel 2, the settings of bits CKEG1 and CKEG0 and TPSC2
to TPSC0 in TCR2 are ignored.
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0
1
0
0
0
0
0
0
0

R/W
R/W
R/W R/W
R/W
R/W R/W
Timer prescaler 2 to 0
These bits select the
counter clock
Clock edge 1, 0
These bits select external clock edges
Counter clear 1, 0
These bits select the counter clear source
Reserved bit
Each TCR is an 8-bit readable/writable register that selects the timer counter clock source, selects
the edge or edges of external clock sources, and selects how the counter is cleared.
TCR is initialized to H'80 by a reset and in standby mode.
Bit 7—Reserved: Read-only bit, always read as 1.
Rev. 3.00 Sep 27, 2006 page 345 of 872
REJ09B0325-0300