HD64F3048VTF8 Datasheet, PDF (207/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 7 Refresh Controller
Set area 3 for 16-bit access
Set P8₁ DDR to 1 for CS₃ output
Set RTCOR
Set bits CKS2 to CKS0 in RTMCSR
Write H'23 in RFSHCR
Wait for DRAM to be initialized
DRAM can be accessed
Figure 7.8 Setup Procedure for 2WE 1-Mbit DRAM (1-Mbyte Mode)
Rev. 3.00 Sep 27, 2006 page 179 of 872
REJ09B0325-0300