HD64F3048VTF8 Datasheet, PDF (168/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 6 Bus Controller
Bus cycle
T₁
T₂
T₃
φ
Address bus
CS _n
Odd external address in area n
AS
RD
Read
access
D₁₅ to D₈
D₇ to D ₀
HWR
High
Invalid
Valid
Write
access
LWR
D₁₅ to D₈
Undetermined data
D₇ to D ₀
Valid
Note: n = 7 to 0
Figure 6.7 Bus Control Signal Timing for 16-Bit, Three-State-Access Area (2)
(Byte Access to Odd Address)
Rev. 3.00 Sep 27, 2006 page 140 of 872
REJ09B0325-0300