HD64F3048VTF8 Datasheet, PDF (225/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 7 Refresh Controller
Bus-released state Refresh cycle CPU cycle Refresh cycle
φ
RFSH
Refresh
request
BACK
Figure 7.24 Refresh Cycles when Bus Is Released
• If a bus cycle is prolonged by insertion of wait states, the first refresh request is held, as in the
bus-released state.
• If there is contention with a bus request from an external bus master when making a transition
to software standby mode, a one-state bus-released state may occur immediately before the
transition to software standby mode (see figure 7.25).
When using software standby mode, clear the BRLE bit to 0 in BRCR before executing the
SLEEP instruction.
When making a transition to self-refresh mode, the strobe waveform output may not be
guaranteed due to the same kind of contention. This, too, can be prevented by clearing the
BRLE bit to 0 in BRCR.
External bus Software standby mode
released state
φ
BREQ
BACK
Address bus
Strobe
Figure 7.25 Contention between Bus-Released State and Software Standby Mode
Rev. 3.00 Sep 27, 2006 page 197 of 872
REJ09B0325-0300