HD64F3048VTF8 Datasheet, PDF (472/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 12 Watchdog Timer
12.2.2 Timer Control/Status Register (TCSR)
TCSR is an 8-bit readable and writable* register. Its functions include selecting the timer mode
and clock source.
Note: * TCSR differs from other registers in being more difficult to write. For details see
section 12.2.4, Notes on Register Rewriting.
Bit
7
6
5
4
OVF WT/IT TME

Initial value
0
0
0
1
Read/Write R/(W)^* R/W R/W

3
2
1
0

CKS2 CKS1 CKS0
1
0
0
0

R/W
R/W
R/W
Clock select
These bits select the
TCNT clock source
Reserved bits
Timer enable
Selects whether TCNT runs or halts
Timer mode select
Selects the mode
Overflow flag
Status flag indicating overflow
Note: * Only 0 can be written, to clear the flag.
Bits 7 to 5 are initialized to 0 by a reset and in standby mode. Bits 2 to 0 are initialized to 0 by a
reset. In software standby mode bits 2 to 0 are not initialized, but retain their previous values.
Bit 7—Overflow Flag (OVF): This status flag indicates that the timer counter has overflowed
from H'FF to H'00.
Bit 7: OVF
0
1
Description
[Clearing condition]
Cleared by reading OVF when OVF = 1, then writing 0 in OVF
[Setting condition]
Set when TCNT changes from H'FF to H'00
(Initial value)
Rev. 3.00 Sep 27, 2006 page 444 of 872
REJ09B0325-0300