HD64F3048VTF8 Datasheet, PDF (189/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

7.1.2 Block Diagram
Figure 7.1 shows a block diagram of the refresh controller.
φ/2, φ/8, φ/32,
φ/128, φ/512,
φ/2048, φ/4096
Refresh signal
Clock selector
Comparator
Control logic
Section 7 Refresh Controller
CMI interrupt
Module data bus
Legend:
RTCNT: Refresh timer counter
RTCOR: Refresh time constant register
RTMCSR: Refresh timer control/status register
RFSHCR: Refresh control register
Figure 7.1 Block Diagram of Refresh Controller
Rev. 3.00 Sep 27, 2006 page 161 of 872
REJ09B0325-0300