 English |
|
|
|
|
|
|
|
| HD64F3048VTF8 Datasheet, PDF (726/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip | |||
| |||
| ◁ |
Section 21 Electrical Characteristics
T1
Ï
tAD
T2
T3
A23 to A0
AS
CS3
RD (read)
D15 to D0
(read)
HWR, LWR
(write)
D15 to D0
(write)
tRAD1
tAS1
tRSD
tWSD
tWDS2
tRAD3
tRP
tSD
tRDS
tRDH
tSD
RFSH
Figure 21.16 PSRAM Bus Timing (Read/Write): Three-State Access
T1
T2
T3
Ï
A23 to A0
AS
CS3 HWR,
LWR, RD
RFSH
tRAD2
tRAD3
Figure 21.17 PSRAM Bus Timing (Refresh Cycle): Three-State Access
Rev. 3.00 Sep 27, 2006 page 698 of 872
REJ09B0325-0300
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese