HD64F3048VTF8 Datasheet, PDF (31/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 1 Overview
Feature
Description
Refresh
controller
• DRAM refresh
 Directly connectable to 16-bit-wide DRAM
 CAS-before-RAS refresh
 Self-refresh mode selectable
• Pseudo-static RAM refresh
 Self-refresh mode selectable
• Usable as an interval timer
DMA controller
(DMAC)
• Short address mode
 Maximum four channels available
 Selection of I/O mode, idle mode, or repeat mode
 Can be activated by compare match/input capture A interrupts from ITU
channels 0 to 3, transmit-data-empty and receive-data-full interrupts from
SCI channel 0, or external requests
• Full address mode
 Maximum two channels available
 Selection of normal mode or block transfer mode
 Can be activated by compare match/input capture A interrupts from ITU
channels 0 to 3, external requests, or auto-request
16-bit integrated • Five 16-bit timer channels, capable of processing up to 12 pulse outputs or
timer unit (ITU)
10 pulse inputs
• One 16-bit timer counter (channels 0 to 4)
• Two multiplexed output compare/input capture pins (channels 0 to 4)
• Operation can be synchronized (channels 0 to 4)
• PWM mode available (channels 0 to 4)
• Phase counting mode available (channel 2)
• Buffering available (channels 3 and 4)
• Reset-synchronized PWM mode available (channels 3 and 4)
• Complementary PWM mode available (channels 3 and 4)
• DMAC can be activated by compare match/input capture A interrupts
(channels 0 to 3)
Rev. 3.00 Sep 27, 2006 page 3 of 872
REJ09B0325-0300