HD64F3048VTF8 Datasheet, PDF (612/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 18 ROM (H8/3048F-ONE: Single Power Supply, H8/3048B Mask ROM Version)
18.4 Flash Memory Register Configuration
The registers* used to control the on-chip flash memory when enabled are shown in table 18.3.
Note: * Access is prohibited to lower 16 address bits H'FF43 to H'FF46 and H'FF48 to H'FF4F.
These bits are designed for the on-chip flash memory version and do not exist in the
on-chip mask ROM version.
In the on-chip mask ROM version, these bits always read 1, and writing is disabled.
Table 18.3 Register Configuration
Register Name
Abbreviation R/W
Initial Value Address^*1
Flash memory control register 1
FLMCR1^*5
R/W^*2
H'00^*3
H'FF40
Flash memory control register 2
FLMCR2^*5
R/W^{*2 *6} H'00
H'FF41
Erase block register
EBR^*5
R/W^*2
H'00^*4
H'FF42
RAM control register
RAMCR^*5
R/W
H'F0
H'FF47
Notes: 1. Lower 16 bits of the address.
2. If the chip is in a mode in which the on-chip flash memory is disabled, a read will return
H'00 and writes are invalid. Writes are also invalid when the FWE bit in FLMCR1 is not
set to 1.
3. When a high level is input to the FWE pin, the initial value is H'80.
4. When a low level is input to the FWE pin, or if a high level is input and the SWE bit in
FLMCR1 is 0, these registers are initialized to H'00.
5. FLMCR1, FLMCR2, EBR, and RAMCR are 8-bit registers.
Byte access must be used on these registers (do not use word or longword access).
6. Bits 6 to 0 are reserved bits but are readable/writable.
18.5 Flash Memory Register Descriptions
18.5.1 Flash Memory Control Register 1 (FLMCR1)
Bit
7
6
5
4
3
2
1
0
FWE
SWE
ESU
PSU
EV
PV
E
P
Initial value
—^*
0
0
0
0
0
0
0
Read/Write
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note: * Determined by the state of the FWE pin.
Rev. 3.00 Sep 27, 2006 page 584 of 872
REJ09B0325-0300