HD64F3048VTF8 Datasheet, PDF (13/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Item
Page
13.3.3 Multiprocessor 495
Communication
Figure 13.11
Example of SCI
Transmit Operation
(8-Bit Data with
Multiprocessor Bit and
One Stop Bit)
13.3.4 Synchronous 500
Operation
Clock
14.2.3 Serial Mode 521
Register (SMR)
Bit 7—GSM Mode
(GM)
18.5.1 Flash Memory 587
Control Register 1
(FLMCR1)
Bit 1—Erase Bit (E)
Section 21 Electrical 653,
Characteristics
654
Table 21.1 Electrical
Characteristics of
H8/3048 Group and
H8/3048B Group
Products
Revision (See Manual for Details)
Figure amended
Multi-
processor
bit
Multi-
processor
bit
Start
1
bit
Data
Stop Start
bit bit
Data
Stop
bit
1
0 D0 D1
D7 0/1 1 0 D0 D1
D7 0/1 1
Idle (mark)
state
TDRE
TEND
TXI
request
TXI interrupt handler
writes data in TDR and
clears TDRE flag to 0
1 frame
TXI
request
TEI request
Description amended
An internal clock generated by the on-chip baud rate
generator or an external clock input from the SCK pin can be
selected by setting the C/A bit in SMR and the CKE1 and
CKE0 bits in SCR. See table 13.9.
Table amended
Bit 7: GM
0
1
Description
Using the regular smart card interface mode
• The TEND flag is set 12.5 etu after the beginning of the start bit
• Clock output on/off control only
Using the GSM mode smart card interface mode
• The TEND flag is set 11.0 etu after the beginning of the start bit
• Clock output on/off and fixed-high/fixed-low control
(set by SCR)
(Initial value)
Note amended
Note: * Do not access flash memory while the E bit is set to 1.
Table amended
Item
Absolute
maximum
ratings
Flash
memory
charac-
teristics^*4
V_PP pin rating
H8/3048B Group
H8/3048
ZTAT
H8/3048
F-ONE
(Single
Power
Supply)
H8/3048B
Mask
ROM
Yes
—
—
—
See table
—
21.11
Rev. 3.00 Sep 27, 2006 page xi of xxvi