HD64F3048VTF8 Datasheet, PDF (820/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Appendix B Internal I/O Register
TSR3—Timer Status Register 3
H'85
ITU3
Bit
7

Initial value
1
Read/Write

6
5


1
1


4
3
2
1
0


OVF IMFB IMFA
1
1
0
0
0

 R/(W)* R/(W)* R/(W)*
Overflow flag
Bit functions are the
same as for ITU0
0 [Clearing condition]
Read OVF when OVF = 1, then write 1 in OVF
1 [Setting condition]
TCNT overflowed from H'FFFF to H'0000 or underflowed from
H'0000 to H'FFFF
Note: * Only 0 can be written, to clear the flag.
TCNT3 H/L—Timer Counter 3 H/L
H'86, H'87
ITU3
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value
Read/Write
00 0000000000 0000
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Complementary PWM mode: up/down counter
Other modes:
up-counter
GRA3 H/L—General Register A3 H/L
H'88, H'89
ITU3
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value
Read/Write
11 1111111111 1111
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Output compare or input capture register (can be buffered)
Rev. 3.00 Sep 27, 2006 page 792 of 872
REJ09B0325-0300