HD64F3048VTF8 Datasheet, PDF (122/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 5 Interrupt Controller
5.2 Register Descriptions
5.2.1 System Control Register (SYSCR)
SYSCR is an 8-bit readable/writable register that controls software standby mode, selects the
action of the UI bit in CCR, selects the NMI edge, and enables or disables the on-chip RAM.
Only bits 3 and 2 are described here. For the other bits, see section 3.3, System Control Register
(SYSCR).
SYSCR is initialized to H'0B by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit
7
6
5
4
3
2
1
0
SSBY STS2 STS1 STS0 UE NMIEG  RAME
Initial value
0
0
0
0
1
0
1
1
Read/Write
R/W
R/W R/W R/W R/W R/W

R/W
Standby timer
select 2 to 0
Software standby
RAM enable
Reserved bit
NMI edge select
Selects the NMI input edge
User bit enable
Selects whether to use the UI bit in
CCR as a user bit or interrupt mask bit
Rev. 3.00 Sep 27, 2006 page 94 of 872
REJ09B0325-0300