HD64F3048VTF8 Datasheet, PDF (566/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 14 Smart Card Interface
Use the following procedure to secure the clock duty cycle after powering on.
1. The initial state is port input and high impedance. Use pull-up or pull-down resistors to fix the
potential.
2. Fix at the output specified by the CKE1 bit in SCR.
3. Set SMR and SCMR, and switch to smart card interface mode operation.
4. Set the CKE0 bit in SCR to 1 to start clock output.
14.4 Usage Notes
When using the SCI as a smart card interface, note the following points.
Receive Data Sampling Timing in Smart Card Mode and Receive Margin
In smart card mode the SCI operates on a base clock with 372 times the bit rate frequency. In
receiving, the SCI synchronizes internally with the fall of the start bit, which it samples on the
base clock. Receive data is latched at the rising edge of the 186th base clock pulse. See figure
14.10.
372 clocks
186 clocks
0
185
371 0
185
371 0
Internal
base clock
Receive data
Start
(RxD)
bit
D0
D1
Synchronization
sampling timing
Data sampling
timing
Figure 14.10 Receive Data Sampling Timing in Smart Card Mode
Rev. 3.00 Sep 27, 2006 page 538 of 872
REJ09B0325-0300