HD64F3048VTF8 Datasheet, PDF (540/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 13 Serial Communication Interface
Restrictions on Usage of the Serial Clock
When transmitting data using an external clock as the serial clock, an interval of at least 5 states is
necessary between clearing the TDRE bit in SSR and the start (falling edge) of the first transmit
clock pulse corresponding to each frame (see figure 13.22). This condition is also needed for
continuous transmission. If it is not fulfilled, operational error will occur.
SCK
t*
t*
TDRE
TXD
X0 X1 X2 X3 X4 X5 X6 X7 Y0 Y1 Y2 Y3
Continuous transmission
Note: * Ensure that t ≥ 5 states.
Figure 13.22 Serial Clock Transmission (Example)
Rev. 3.00 Sep 27, 2006 page 512 of 872
REJ09B0325-0300