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HD64F3048VTF8 Datasheet, PDF (273/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip | |||
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Section 8 DMA Controller
Figure 8.17 shows the timing when the DMAC is activated by level-sensitive low DREQ input in
normal mode.
CPU cycle
DMAC cycle
CPU cycle
T2 T1 T2 T1 T2 Td T1 T2 T1 T2 T1 T2 T1 T2 T 1
Ï
DREQ
Address
bus
RD
HWR , LWR
Minimum 4 states
Next sampling point
Figure 8.17 Timing of DMAC Activation by Low DREQ Level in Normal Mode
Rev. 3.00 Sep 27, 2006 page 245 of 872
REJ09B0325-0300
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