HD64F3048VTF8 Datasheet, PDF (22/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

11.2.1 Port A Data Direction Register (PADDR) ........................................................... 419
11.2.2 Port A Data Register (PADR) .............................................................................. 419
11.2.3 Port B Data Direction Register (PBDDR)............................................................ 420
11.2.4 Port B Data Register (PBDR) .............................................................................. 420
11.2.5 Next Data Register A (NDRA) ............................................................................ 421
11.2.6 Next Data Register B (NDRB)............................................................................. 423
11.2.7 Next Data Enable Register A (NDERA).............................................................. 425
11.2.8 Next Data Enable Register B (NDERB) .............................................................. 426
11.2.9 TPC Output Control Register (TPCR) ................................................................. 427
11.2.10 TPC Output Mode Register (TPMR) ................................................................... 429
11.3 Operation .......................................................................................................................... 431
11.3.1 Overview.............................................................................................................. 431
11.3.2 Output Timing...................................................................................................... 432
11.3.3 Normal TPC Output............................................................................................. 433
11.3.4 Non-Overlapping TPC Output ............................................................................. 435
11.3.5 TPC Output Triggering by Input Capture ............................................................ 437
11.4 Usage Notes ...................................................................................................................... 438
11.4.1 Operation of TPC Output Pins ............................................................................. 438
11.4.2 Note on Non-Overlapping Output........................................................................ 438
Section 12 Watchdog Timer............................................................................................. 441
12.1 Overview........................................................................................................................... 441
12.1.1 Features................................................................................................................ 441
12.1.2 Block Diagram ..................................................................................................... 442
12.1.3 Pin Configuration................................................................................................. 442
12.1.4 Register Configuration......................................................................................... 443
12.2 Register Descriptions ........................................................................................................ 443
12.2.1 Timer Counter (TCNT)........................................................................................ 443
12.2.2 Timer Control/Status Register (TCSR) ................................................................ 444
12.2.3 Reset Control/Status Register (RSTCSR) ............................................................ 446
12.2.4 Notes on Register Rewriting ................................................................................ 447
12.3 Operation .......................................................................................................................... 449
12.3.1 Watchdog Timer Operation ................................................................................. 449
12.3.2 Interval Timer Operation ..................................................................................... 450
12.3.3 Timing of Setting of Overflow Flag (OVF) ......................................................... 450
12.3.4 Timing of Setting of Watchdog Timer Reset Bit (WRST) .................................. 451
12.4 Interrupts ........................................................................................................................... 452
12.5 Usage Notes ...................................................................................................................... 452
12.6 Notes ................................................................................................................................. 453
Rev. 3.00 Sep 27, 2006 page xx of xxvi