HD64F3048VTF8 Datasheet, PDF (809/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

TFCR—Timer Function Control Register
Appendix B Internal I/O Register
H'63 ITU (all channels)
Bit
7

Initial value
1
Read/Write

6
5
4
3
2
1
0
 CMD1 CMD0 BFB4 BFA4 BFB3 BFA3
1
0
0
0
0
0
0

R/W R/W R/W R/W R/W R/W
Buffer mode A3
0 GRA3 operates normally
1 GRA3 is buffered by BRA3
Buffer mode B3
0 GRB3 operates normally
1 GRB3 is buffered by BRB3
Buffer mode A4
0 GRA4 operates normally
1 GRA4 is buffered by BRA4
Buffer mode B4
0 GRB4 operates normally
1 GRB4 is buffered by BRB4
Combination mode 1 and 0
Bit 5 Bit 4
CMD1 CMD0 Operating Mode of Channels 3 and 4
0
0 Channels 3 and 4 operate normally
1
1
0 Channels 3 and 4 operate together in complementary PWM mode
1 Channels 3 and 4 operate together in reset-synchronized PWM mode
Rev. 3.00 Sep 27, 2006 page 781 of 872
REJ09B0325-0300