HD64F3048VTF8 Datasheet, PDF (165/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 6 Bus Controller
6.3.4 Bus Control Signal Timing
8-Bit, Three-State-Access Areas
Figure 6.4 shows the timing of bus control signals for an 8-bit, three-state-access area. The upper
address bus (D₁₅ to D₈) is used to access these areas. The LWR pin is always high. Wait states can
be inserted.
Bus cycle
T₁
T₂
T₃
φ
Address bus
CS _n
External address in area n
AS
RD
Read
access
D₁₅ to D₈
D₇ to D ₀
HWR
Valid
Invalid
Write
access
LWR
D₁₅ to D₈
High
Valid
D₇ to D ₀
Undetermined data
Note: n = 7 to 0
Figure 6.4 Bus Control Signal Timing for 8-Bit, Three-State-Access Area
Rev. 3.00 Sep 27, 2006 page 137 of 872
REJ09B0325-0300