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HD64F3048VTF8 Datasheet, PDF (710/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip
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Section 21 Electrical Characteristics
21.2.3 AC Characteristics
Bus timing parameters are listed in table 21.15. Refresh controller bus timing parameters are listed
in table 21.16. Control signal timing parameters are listed in table 21.17. Timing parameters of the
on-chip supporting modules are listed in table 21.18.
Table 21.15 Bus Timing
Condition A: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, VREF = 3.0 V to AVCC,
VSS = AVSS = 0 V, φ = 2 MHz to 25 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
Condition B: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, VREF = 4.5 V to AVCC,
VSS = AVSS = 0 V, φ = 2 MHz to 25 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
Item
Symbol
Clock cycle time
tcyc
Clock pulse low width
tCL
Clock pulse high width
tCH
Clock rise time
tCR
Clock fall time
tCF
Address delay time
tAD
Address hold time
tAH
Address strobe delay time tASD
Write strobe delay time tWSD
Strobe delay time
tSD
Write data strobe pulse tWSW1
width 1
Write data strobe pulse tWSW2
width 2
Address setup time 1
tAS1
Address setup time 2
tAS2
Read data setup time
tRDS
Read data hold time
tRDH
Condition A
25 MHz
Min
Max
40
500
10
—
10
—
—
10
—
10
—
28
0.5tcyc –20 —
—
25
—
25
—
25
1.0tcyc –25 —
1.5tcyc –25 —
0.5tcyc –20 —
1.0tcyc –20 —
15
—
0
—
Condition B
25 MHz
Min
Max
40
500
10
—
10
—
—
10
—
10
—
25
0.5tcyc –20 —
—
25
—
25
—
25
1.0tcyc –25 —
1.5tcyc –25 —
0.5tcyc –20 —
1.0tcyc –20 —
15
—
0
—
Test
Unit Conditions
ns Figure 21.7
Figure 21.8
Rev. 3.00 Sep 27, 2006 page 682 of 872
REJ09B0325-0300
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