MEC1404 Datasheet, PDF (99/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
4.0 LPC INTERFACE
4.1 Introduction
The Intel® Low Pin Count (LPC) Interface is the LPC Interface used by the system host to configure the chip and com-
municate with the logical devices implemented in the design through a series of read/write registers. Register access is
accomplished through the LPC transfer cycles defined in Table 4-5, "LPC Cycle Types Supported".
The Logical Devices implemented in the design are identified in Table 4-14, “I/O Base Address Registers,” on page 122.
The Base Address Registers allow any logical device’s runtime registers to be relocated in LPC I/O space. All chip con-
figuration registers for the device are accessed indirectly through the LPC I/O Configuration Port (see Section 4.8.3,
"Configuration Port," on page 110).
4.2 References
• Intel® Low Pin Count (LPC) Interface Specification, v1.1
• PCI Local Bus Specification, Rev. 2.2
• Serial IRQ Specification for PCI Systems Version 6.0.
• PCI Mobile Design Guide Rev 1.0
4.3 Terminology
This table defines specialized terms localized to this feature.
TABLE 4-1: TERMINOLOGY
Term
System Host
Logical Devices
Runtime Register
Configuration Registers
EC_Only Registers
Definition
Refers to the external CPU that communicates with this device via the LPC Inter-
face.
Logical Devices are LPC accessible features that are allocated a Base Address and
range in LPC I/O address space
Runtime Registers are register that are directly I/O accessible by the System Host
via the LPC interface. These registers are defined in Section 4.10, "Runtime Regis-
ters," on page 125.
Registers that are only accessible in CONFIG_MODE. These registers are defined
in Section 4.9, "LPC Configuration Registers," on page 117.
Registers that are not accessible by the System Host. They are only accessible by
an internal embedded controller. These registers are defined in Section 4.11, "EC-
Only Registers," on page 126.
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