MEC1404 Datasheet, PDF (227/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
14.8 Interrupts
This section defines the Interrupt Sources generated from this block.
OBF
IBF
Source
Description
OBF interrupt is asserted when the OBF in the EC STATUS Register is
cleared to ‘0’.
IBF interrupt is asserted when the IBF in the EC STATUS Register is set
to ‘1’.
Note:
The usage model from the ACPI specification requires both SMI’s and SCI’s. The ACPI_OS SMI & SCI
interrupts are not implemented in the ACPI Embedded Controller Interface (ACPI-ECI). The SMI_EVT and
SCI_EVT bits in the OS STATUS OS Register are software flags and this block do not initiate SMI or SCI
events.
14.9 Low Power Modes
The ACPI Embedded Controller Interface (ACPI-ECI) automatically enters low power mode when no transaction targets
it.
14.10 Description
The ACPI Embedded Controller Interface (ACPI-ECI) provides an APCI-EC interface that adheres to the ACPI specifi-
cation. The ACPI Embedded Controller Interface (ACPI-ECI) includes two modes of operation: Legacy Mode and Four-
byte Mode.
The ACPI Embedded Controller Interface (ACPI-ECI) defaults to Legacy Mode which provides single byte Full Duplex
operation. Legacy Mode corresponds to the ACPI specification functionality as illustrated in FIGURE 14-2: on page 228.
The EC interrupts in FIGURE 14-2: on page 228 are implemented as OBF & IBF. See Section 14.8, "Interrupts," on
page 227.
In Four-byte Mode, the ACPI Embedded Controller Interface (ACPI-ECI) provides four byte Full Duplex operation. Four-
byte Mode is a superset of the ACPI specification functionality as illustrated in FIGURE 14-2: on page 228.
Both Legacy Mode & Four-byte Mode provide Full Duplex Communications which allows data/command transfers in
one direction while maintaining data from the other direction; communications can flow both ways simultaneously.
In Legacy Mode, ACPI Embedded Controller Interface (ACPI-ECI) contains three registers: ACPI OS COMMAND Reg-
ister, OS STATUS OS Register, and OS2EC Data EC Byte 0 Register. The standard ACPI Embedded Controller Inter-
face (ACPI-ECI) registers occupy two addresses in the ACPI_OS space (TABLE 14-5:).
The OS2EC Data EC Byte 0 Register and ACPI OS COMMAND Register registers appear as a single 8-bit data register
in the ACPI_EC. The CMD bit in the OS STATUS OS Register is used by the ACPI_EC to discriminate commands from
data written by the ACPI_OS to the ACPI_EC. CMD bit is controlled by hardware: ACPI_OS writes to the OS2EC Data
EC Byte 0 Register register clear the CMD bit; ACPI_OS writes to the ACPI OS COMMAND Register set the CMD bit.
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