MEC1404 Datasheet, PDF (451/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
TABLE 37-2: INTERNAL SIGNAL DESCRIPTION TABLE
Name
POWER_UP_EVENT
VTRGD
Direction
INPUT
INPUT
Description
Signal from the RTC/Week Timer block. The POW-
ER_UP_EVENT is asserted by the timer when either the
Week_Alarm or the Sub-Week Alarm is asserted. The POW-
ER_UP_EVENT can be suppressed if the SYSPWR_PRES pin
indicates that system power is not available.
Status signal for the state of the VTR power rail. This signal is high
if the power rail is on, and low if the power rail is off.
37.4 Host Interface
The registers defined for the VBAT-Powered Control Interface are accessible only by the EC.
37.5 Power, Clocks and Resets
This section defines the Power, Clock, and Reset parameters of the block.
37.5.1 POWER DOMAINS
TABLE 37-3:
POWER SOURCES
Name
VBAT
VTR
37.5.2 CLOCKS
This block does not require clocks.
Description
This power well sources all of the internal registers and logic in this block.
This power well sources only bus communication. The block continues to
operate internally while this rail is down.
37.5.3 RESETS
TABLE 37-4: RESET SIGNALS
Name
VBAT_POR
nSYSRST
37.6 Interrupts
Description
This reset signal is used reset all of the registers and logic in this block.
This reset signal is used to inhibit the bus communication logic, and iso-
lates this block from VTR powered circuitry on-chip. Otherwise it has no
effect on the internal state.
TABLE 37-5:
EC INTERRUPTS
Source
VCI_IN0
Description
This interrupt is routed to the Interrupt Controller It is only asserted when
both VBAT and VTR are powered. Edge detection and assertion level for
the interrupt are configured in the GPIO Pin Control Register for the GPIO
that shares the pin with VCI_IN# input. This interrupt is equivalent to the
GPIO interrupt for the GPIO that shares the pin, but appears on a differ-
ent register in the Interrupt Aggregator.
 2015 - 2016 Microchip Technology Inc.
DS00001956D-page 451