MEC1404 Datasheet, PDF (344/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
23.0 SMBUS INTERFACE
23.1 Introduction
The MEC140X/1X SMBus Interface includes one instance of the SMBus controller core. This chapter describes aspects
of the SMBus Interface that are unique to the MEC140X/1X instantiations of this core; including, Power Domain, Resets,
Clocks, Interrupts, Registers and the Physical Interface. For a General Description, Features, Block Diagram, Func-
tional Description, Registers Interface and other core-specific details, see Ref [1] (note: in this chapter, italicized text
typically refers to SMBus controller core interface elements as described in Ref [1]).
23.2 References
1. SMBus Controller Core with Network Layer Support (SMB2) - 16MHz I2C Baud Clock“, Revision 3.52, Core-
Level Architecture Specification, MCHP, 10/25/13
23.3 Terminology
There is no terminology defined for this chapter.
23.4 Interface
This block is designed to be accessed externally via the pin interface and internally via a registered host interface. In
addition, this block is equipped with
FIGURE 23-1:
I/O DIAGRAM OF BLOCK
Host Interface
DMA Interface
Power, Clocks and Reset
Interrupts
SMBus Interface
Signal Description
23.5 Signal Description
The pin signals are defined in Section 2.0, "Pin Configuration," on page 12.
23.6 Host Interface
The registers defined for the SMBus Interface are accessible as indicated in Section 23.12, "SMBus Registers".
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