MEC1404 Datasheet, PDF (142/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
Offset ^08h
Bits
Description
Type
1 STOP
W
Writing a ‘1’ to this bit will stop any transfer in progress at the next
byte boundary. Writing a ‘0’ to this bit has no effect. This bit is self-
clearing.
This bit must not be set to ‘1’ if the field START in this register is set
to ‘1’.
0 START
W
Writing a ‘1’ to this bit will start the SPI transfer. Writing a ‘0’ to this
bit has no effect. This bit is self-clearing.
This bit must not be set to ‘1’ if the field STOP in this register is set
to ‘1’.
6.11.4 QMSPI INTERFACE CONTROL REGISTER
Default
0h
Reset
Event
RESET
1h
RESET
Offset ^0Ch
Bits
Description
Type
31:8 Reserved
R
7 PULLUP_ON_NOT_DRIVEN
R/W
1=Enable pull-up resistors on Transmit pins while the pins are not
driven
0=No pull-up resistors enabled ion Transmit pins
6 PULLDOWN_ON_NOT_DRIVEN
R/W
1=Enable pull-down resistors on Transmit pins while the pins are
not driven
0=No pull-down resistors enabled ion Transmit pins
5 PULLUP_ON_NOT_SELECTED
R/W
1=Enable pull-up resistors on Receive pins while the SPI Chip
Select signal is not asserted
0=No pull-up resistors enabled on Receive pins
4 PULLDOWN_ON_NOT_SELECTED
R/W
1=Enable pull-down resistors on Receive pins while the SPI Chip
Select signal is not asserted
0=No pull-down resistors enabled on Receive pins
Default
-
0h
Reset
Event
-
RESET
0h
RESET
1h
RESET
0h
RESET
DS00001956D-page 142
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