MEC1404 Datasheet, PDF (526/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
43.20 PS/2 Timing
FIGURE 43-23: PS/2 TRANSMIT TIMING
t2
PS2_CLK
t1
PS2_DAT
PS2_EN
PS2_T/R
XMIT_IDLE
RDATA_RDY
Write Tx Reg
Interrupt
t7
t5
t6
1
2
t8 t9 ^t10
t17
10
11
t4
s
t11
t14
B0
B1 B2 B3 B4
B5 B6 B7
P
t12
t3
t13
t15
Note 1
TABLE 43-24: PS/2 CHANNEL TRANSMISSION TIMING PARAMETERS
Name
Description
MIN
TYP
t1 The PS/2 Channel’s CLK and DATA lines
are floated following PS2_EN=1 and
PS2_T/R=0.
t2 PS2_T/R bit set to CLK driven low pre-
paring the PS/2 Channel for data trans-
mission.
t3 CLK line floated to XMIT_IDLE bit de-
asserted.
t4 Trailing edge of WR to Transmit Register
to DATA line driven low.
t5 Trailing edge of EC WR of Transmit Reg-
ister to CLK line floated.
t6 Initiation of Start of Transmit cycle by the
PS/2 channel controller to the auxiliary
peripheral’s responding by latching the
Start bit and driving the CLK line low.
t7 Period of CLK
t8 Duration of CLK high (active)
t9 Duration of CLK low (inactive)
45
90
0.002
60
30
MAX
1000
1.7
90
130
25.003
302
151
Units
ns
ns
ms
µs
DS00001956D-page 526
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