MEC1404 Datasheet, PDF (162/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
8.9.1 POWER ON RESET
Following a power on reset event the EC_PROC_RESET# signal is de-asserted and the embedded controller starts
executing code from the first physical address of the Boot ROM.
8.9.2 INSTRUCTION SET
The M14K core defaults to the microMIPS instruction set and is runtime configurable as either microMIPS Instruction
set.
This device does not support the following atomic instructions. A critical section should be used instead of these
instructions. NOTE: A critical section will not protect a memory location from DMA access.
LL – Load Linked Word. LL and SC must be used together to implement an atomic transaction.
SC – Store Conditional Word
ACLR – Atomically Clear Bit within Byte
ASET - Atomically Set Bit within Byte
The device does not support the following interrupt return instruction. This instruction requires additional shadow regis-
ter set. Use ERET instead.
IRET – Interrupt Return with automated interrupt epilog handling.
8.9.3 EJTAG HARDWARE DEBUG BREAK POINTS
This M14K core is configured for two data and four instruction breakpoints, without complex breakpoints
8.9.4 GENERAL PURPOSED REGISTER (GPR) SHADOW REGISTERS
The M14K core contains thirty-two 32-bit general-purpose registers used for integer operations and address calculation.
No optional register sets were implemented.
8.9.5 MULTIPLY/DIVIDE UNIT (MDU)
This device is configured for the higher performance 32x16 array option.
8.9.6 SYSTEM CONTROL COPROCESSOR (CP0)
8.9.6.1 System Interface
The System Interface signals are defined in the Interfaces section. See Section 8.4.3, "System Interface," on page 159.
8.9.6.2 Interrupt Handling
This device is configured for External Interrupt Controller (EIC) mode.
8.9.7 MEMORY MANAGEMENT UNIT (MMU)
The M14K core implements a simple Fixed Mapping (FM) memory management unit.
DS00001956D-page 162
 2015 - 2016 Microchip Technology Inc.