MEC1404 Datasheet, PDF (190/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
TABLE 10-7: GIRQX ENABLE CLEAR REGISTER FORMAT
Offset ^{See Table 10-4, "JTVIC Register Summary"}
Bits
Description
Type
31:9 Reserved
30:0 GIRQx Enable Clear[31:0]
Each GIRQx bit can be individually disabled to assert an interrupt
event.
0= Writing a zero has no effect.
1= Writing a one will disable respective GIRQx.
R
R/WC
Default
-
0h
Reset
Event
-
nSYSR
ST
Reading always returns the current value of the GIRQx ENABLE bit.
The state of the GIRQx ENABLE bit is determined by the correspond-
ing GIRQx Enable Set bit and the GIRQx Enable Clear bit. (0=dis-
abled, 1-enabled)
Note:
For GIRQx Bit Assignments see Table 10-2, “Interrupt
Source, Enable Set, Enable Clear, and Result Bit Assign-
ments,” on page 169. Unassigned bits are Reserved;
Reads return 0.
TABLE 10-8: GIRQX RESULT REGISTER FORMAT
Offset ^{See Table 10-4, "JTVIC Register Summary"}
Bits
Description
31 Bit D31 is hard-coded to ‘1’.
30:0 GIRQx Interrupt Result
The GIRQx Result bits are Read-Only status bits indicating the state
of interrupt after the interrupt enable bit.
Type
R
R
Note:
For GIRQx Bit Assignments see Table 10-2, “Interrupt
Source, Enable Set, Enable Clear, and Result Bit Assign-
ments,” on page 169. Unassigned bits are Reserved;
Reads return 0.
Default
1h
0h
Reset
Event
-
nSYSR
ST
10.12.2 AGGREGATOR CONTROL REGISTERS
TABLE 10-9: GIRQX AGGREGATOR CONTROL REGISTER FORMAT
Offset ^-
Bits
Description
31:18 Reserved
17:1 Aggregator Vector Address
• In Aggregated Mode the Aggregated Vector Address is added to
the processor EBASE to determine the physical jump address.
• In Disaggregated Mode this is used as part of the calculation to
determine the Jump Table Vector physical address. See JTEn-
able (Jump-Table Enable) bit description.
Type
R
R/W
Default
-
00h
Reset
Event
-
nSYSR
ST
DS00001956D-page 190
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