MEC1404 Datasheet, PDF (366/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
25.10 Instance Description
There is one instance of the PECI Core implemented in the PECI Interface in the MEC140X/1X. See PECI Interface
Core, Rev. 1.31, Core-Level Architecture Specification, SMSC Confidential, 4/15/11 for a description of the PECI Core.
25.11 PECI Interface Registers
The registers listed in the PECI Interface Register Summary table are for a single instance of the PECI Interface. The
addresses of each register listed in this table are defined as a relative offset to the host “Base Address” defined in the
PECI Interface Register Base Address Table.
TABLE 25-3: EC-ONLY REGISTER BASE ADDRESS TABLE
Block Instance
PECI Interface
Instance
Number
0
Host
EC
Address Space
32-bit Internal
Address Space
Base Address
0000_6400h
Note: The Base Address indicates where the first register can be accessed in a particular address space for a
block instance.
TABLE 25-4: PECI INTERFACE REGISTER SUMMARY
Offset
00h
04h
08h
0Ch
10h
14h
18h
1Ch
20h
24h
28h
2Ch
30h-3Ch
40h
44h
48h - 7Ch
Register Name (Mnemonic)
Write Data Register
Read Data Register
Control Register
Status Register 1
Status Register 2
Error Register
Interrupt Enable 1 Register
Interrupt Enable 2 Register
Optimal Bit Time Register (Low Byte)
Optimal Bit Time Register (High Byte)
Test
Test
Reserved
Block ID Register
Revision Register
Test
DS00001956D-page 366
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