MEC1404 Datasheet, PDF (404/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
The interface is enabled by the PS2_EN bit. Transfers are enabled when PS2_EN is ‘1’ and disabled when PS2_EN is
‘0’. If the PS2_EN bit is cleared to ‘0’ while a transfer is in progress but prior to the leading edge (falling edge) of the
10th (parity bit) clock edge, the receive data is discarded (RDATA_RDY remains low). If the PS2_EN bit is cleared fol-
lowing the leading edge of the 10th clock signal, then the receive data is saved in the Receive Register (RDATA_RDY
goes high) assuming no parity error.
The direction of a PS/2 transfer is controlled by the PS2_T/R bit.
29.13.1 RECEIVE
If PS2_T/R is ‘0’ while the PS2 Interface is enabled, the interface is configured to receive data. If while PS2_T/R is ‘0’
RDATA_RDY is ‘0’, the channel’s PS2_CLK and PS2_DAT will float waiting for the external PS/2 device to signal the
start of a transmission. If RDATA_RDY is ‘1’, the channel’s PS2_DAT line will float but its PS2_CLK line will be held low,
holding off the peripheral, until the Receive Register is read.
The peripheral initiates a reception by sending a start bit followed by the data bits). After a successful reception, data
are placed in the PS2 Receive Buffer Register, the RDATA_RDY bit in the PS2 Status Register is set and the PS2_CLK
line is forced low. Further receive transfers are inhibited until the EC reads the data in the PS2 Receive Buffer Register.
RDATA_RDY is cleared and the PS2_CLK line is tri-stated following a read of the PS2 Receive Buffer Register.
The Receive Buffer Register is initialized to FFh after a read or after a Time-out has occurred.
29.13.2 TRANSMIT
If PS2_T/R is ‘1’ while the PS2 Interface is enabled, the interface is configured to transmit data. When the PS2_T/R bit
is written to ‘1’ while the state machine is idle, the channel prepares for a transmission: the interface will drive the PS2_-
CLK line low and then float the PS2_DAT line, holding this state until a write occurs to the Transmit Register or until the
PS2_T/R bit is cleared. A transmission is started by writing the PS2 Transmit Buffer Register. Writes to the Transmit
Buffer Register are blocked when PS2_EN is ‘0’, PS2_T/R is ‘0’ or when the transmit state machine is active (the
XMIT_IDLE bit in the PS/2 Status Register is ‘0’). The transmission of data will not start if there is valid data in the
Receive Data Register (when the status bit RDATA_RDY is ‘1’). When a transmission is started, the transmission state
machine becomes active (the XMIT_IDLE bit is set to ‘1’ by hardware), the PS2_DAT line is driven low and within 80ns
the PS2_CLK line floats (externally pulled high by the pull-up resistor).
The transmission terminates either on the 11th clock edge of the transmission or if a Transmit Time-Out error condition
occurs. When the transmission terminates, the PS2_T/R bit is cleared to ‘0’and the state machine becomes idle, setting
XMIT_IDLE to ‘1’.
The PS2_T/R bit must be written to a ‘1’ before initiating another transmission to the remote device. If the PS2_T/R bit
is set to ‘1’ while the channel is actively receiving data (that is, while the status bit RDATA_RDYis ‘1’) prior to the leading
edge of the 10th (parity bit) clock edge, the receive data is discarded. If the bit is set after the 10th edge, the receive
data is saved in the Receive Register.
29.14 Instance Description
29.15 EC-Only Registers
The registers listed in the EC-Only Register Summary table are for a single instance of the PS/2 Interface. The
addresses of each register listed in this table are defined as a relative offset to the host “Base Address” defined in the
EC-Only Register Base Address Table.
TABLE 29-4: EC-ONLY REGISTER BASE ADDRESS TABLE
Block Instance
PS/2 Interface
Instance
Number
0
1
Host
EC
EC
Address Space
32-bit internal
address space
32-bit internal
address space
Base Address
0000_9000h
0000_9040h
The Base Address indicates where the first register can be accessed in a particular address space for a block instance.
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