MEC1404 Datasheet, PDF (311/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
21.6 Interrupts
TABLE 21-6: EC INTERRUPTS
Source
WEEK_ALARM_INT
SUB_WEEK_ALARM_INT
ONE_SECOND
SUB_SECOND
SYSPWR_PRES
Description
This interrupt is signaled to the Interrupt Aggregator when the Week
Alarm Counter Register is greater than or equal to the Week Timer Com-
pare Register. The interrupt signal is always generated by the RTC/Week
Timer if the block is enabled; the interrupt is enabled or disabled in the
Interrupt Aggregator.
This interrupt is signaled to the Interrupt Aggregator when the Sub-Week
Alarm Counter Register decrements from ‘1’ to ‘0’. The interrupt signal is
always generated by the RTC/Week Timer if the block is enabled; the
interrupt is enabled or disabled in the Interrupt Aggregator.
This interrupt is signaled to the Interrupt Aggregator at an isochronous
rate of once per second. The interrupt signal is always generated by the
RTC/Week Timer if the block is enabled; the interrupt is enabled or dis-
abled in the Interrupt Aggregator.
This interrupt is signaled to the Interrupt Aggregator at an isochronous
rate programmable between 0.5Hz and 32.768KHz. The rate interrupts
are signaled is determined by the SPISR field in the Sub-Second Pro-
grammable Interrupt Select Register. See Table 21-10, "SPISR Encod-
ing". The interrupt signal is always generated by the RTC/Week Timer if
the block is enabled; the interrupt is enabled or disabled in the Interrupt
Aggregator.
This wake interrupt is signaled to the Interrupt Aggregator when an Alarm
event occurs. The associated GPIO pin Control Register must be pro-
grammed in order to configure the interrupt condition.
21.7 Low Power Modes
The RTC/Week Alarm has no low-power modes. It runs continuously while the VBAT well is powered.
21.8 Power-Up Events
The RTC/Week Timer POWER_UP_EVENT can be used to power up the system after a timed interval. The POW-
ER_UP_EVENT is routed to the VBAT-Powered Control Interface. The VCI_OUT pin that is part of the VCI is asserted
if the POWER_UP_EVENT is asserted.
The POWER_UP_EVENT can be asserted under the following two conditions:
1. The Week Alarm Counter Register is greater than or equal to the Week Timer Compare Register
2. The Sub-Week Alarm Counter Register decrements from ‘1’ to ‘0’
The assertion of the POWER_UP_EVENT is inhibited by the following two conditions:
1. The POWERUP_EN field in the Control Register is ‘0’
2. The SYSPWR_PRES_ENABLE field in the Sub-Week Control Register is ‘1’ and the SYSPWR_PRES input pin
is ‘0’. This option permits inhibiting a timeout causing a system wake during a deep sleep and draining the battery
if AC Power is not present.
Once a POWER_UP_EVENT is asserted the POWERUP_EN bit must be cleared to reset the output. Clearing
POWERUP_EN is necessary to avoid unintended power-up cycles.
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