MEC1404 Datasheet, PDF (235/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
Offset ^04h
Bits
Description
Type
5 SCI_EVT
R
This bit is set by software when an SCI event is pending; i.e., the
ACPI_EC is requesting an SCI query; SCI Event flag is clear when
no SCI events are pending.
This bit is an ACPI_EC-maintained software flag that is set when
the embedded controller has detected an internal event that
requires operating system attention. The ACPI_EC sets this bit
before generating an SCI to the OS.
Note:
The usage model from the ACPI specification requires
both SMI’s and SCI’s. The ACPI_OS SMI & SCI inter-
rupts are not implemented in the ACPI Embedded
Controller Interface (ACPI-ECI). The SMI_EVT and
SCI_EVT bits in the OS STATUS OS Register are soft-
ware flags and this block do not initiate SMI or SCI
events.
4 BURST
R
The BURST bit is set when the ACPI_EC is in Burst Mode for
polled command processing; the BURST bit is cleared when the
ACPI_EC is in Normal mode for interrupt-driven command pro-
cessing.
The BURST bit is an ACPI_EC-maintained software flag that indi-
cates the embedded controller has received the Burst Enable
command from the host, has halted normal processing, and is
waiting for a series of commands to be sent from the host. Burst
Mode allows the OS or system management handler to quickly
read and write several bytes of data at a time without the over-
head of SCIs between commands.
The BURST bit is maintained by ACPI_EC software, only.
3 CMD
R
This bit is set when the OS2EC Data EC Byte 0 Register contains
a command byte written into ACPI OS COMMAND Register; this
bit is cleared when the OS2EC DATA BYTES[3:0] contains a data
byte written into the ACPI-OS DATA BYTES[3:0].
This bit is hardware controlled:
• ACPI_OS writes to any of the four ACPI-OS DATA
BYTES[3:0] bytes clears this bit
• ACPI_OS writes to the ACPI OS COMMAND Register sets
this bit.
Note:
This bit allows the embedded controller to differentiate
the start of a command sequence from a data byte
write operation.
2 UD1B
R
User Defined
Default
0b
Reset
Event
nSYSR
ST
0b
nSYSR
ST
0b
nSYSR
ST
0b
nSYSR
ST
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DS00001956D-page 235