MEC1404 Datasheet, PDF (300/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
19.5 Power, Clocks and Resets
This section defines the Power, Clock, and Reset parameters of the block.
19.5.1 POWER DOMAINS
NAME
VTR
DESCRIPTION
This power well sources all of the registers and logic in this block.
19.5.2 CLOCKS
This section describes all the clocks in the block, including those that are derived from the I/O Interface as well as the
ones that are derived or generated internally.
NAME
32KHz_Clk
48 MHz Ring Oscillator
19.5.3 RESETS
DESCRIPTION
Timer Clock Source
System Clock used by Host Interface for register access
NAME
nSYSRST
DESCRIPTION
This power on reset (POR) signal resets all of the registers and logic in
this block.
19.6 Interrupt Generation
This section defines the Interrupt Sources generated from this block.
SOURCE
RTOS_TIMER
DESCRIPTION
Note:
The RTOS Timer block generates a pulse anytime the RTOS
Timer transitions from 1 to 0. This pulse is used to generate a
wake-capable interrupt event that is latched by the Jump Table
Vectored Interrupt Controller (JTVIC).
19.7 Low Power Modes
The RTOS Timer may be put into a low power state by the chip Power, Clocks, and Reset (PCR) circuitry.
The timer operates off of the 32KHz_Clk, and therefore will operate normally when 48 MHz Ring Oscillator is stopped.
The sleep enable input has no effect on the RTOS Timer and the clock required output is only asserted during register
read/write cycles for as long as necessary to propagate updates to the block core.
19.7.1 SLEEP INTERFACE - SYSTEM CLOCK
The RTOS Timer is designed to always operate in its lowest functional power consumption state. In addition, it can be
commanded to enter a lower power state via the Sleep Enable signal. The block notifies the chip’s power management
circuitry when it is in its low power state by driving the Clock Required signal low. The following table defines all the
blocks Power States associated with the System Clock.
DS00001956D-page 300
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