MEC1404 Datasheet, PDF (433/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
TABLE 33-1: CONFIGURATION REGISTER SUMMARY
EC Offset
330h
Host Index
30h
Activate Register
Register Name (Mnemonic)
33.10.1 ACTIVATE REGISTER
Offset ^330h
Bits
Description
7:1 Reserved
0 ACTIVATE
When this bit is asserted ‘1’, the block is enabled. When this bit is
‘0’, writes by the Host interface to the Host Data Register are not
claimed, the FIFO is flushed, the 24-bit Timer is reset, and the
timer clock is stopped. Control bits in the Configuration Register
are not affected by the state of ACTIVATE.
Type
R
R/W
Default
-
0h
Reset
Event
-
nSYSR
ST
33.11 Runtime Registers
The registers listed in the Runtime Register Summary table are for two instances of the Port 80 BIOS Debug Port.
The addresses of each register listed in this table are defined as a relative offset to the host “Base Address” defined in
the Runtime Register Base Address Table.
Note: The Runtime registers may be accessed by the EC but typically the Host will access the Runtime Registers
and the EC will access just the EC-Only registers.
TABLE 33-2: RUNTIME REGISTER BASE ADDRESS TABLE
Block Instance
Port 80 BIOS
Debug Port
Instance
Number
0
1
Host
LPC
EC
LPC
EC
Address Space
I/O
32-bit internal
address space
I/O
32-bit internal
address space
Base Address
Programmed BAR
000F_5400h
Programmed BAR
000F_5800h
The Base Address indicates where the first register can be accessed in a particular address space for a block instance.
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DS00001956D-page 433