MEC1404 Datasheet, PDF (87/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
Note:
The System Sleep States shown in TABLE 3-12: are determined by bits 2:0 in this register. The device only
enters these sleep states after all the blocks have been commanded to sleep and they no longer require
the 48 MHz Ring Oscillator; that is, if the sleep enable bits are set for all blocks or the Sleep All bit is set
and no clocks are required.
TABLE 3-12: SYSTEM SLEEP CONTROL BIT ENCODING
D2
D1
D0 Wake Latency
Description
0
0
0
0
The Core regulator and the Ring Oscillator remain powered and run-
ning during sleep cycles (SYSTEM HEAVY SLEEP 1) (DEFAULT)
0
1
0
0
The Core regulator remains powered and the Ring oscillator is run-
ning but gated during sleep cycles (SYSTEM HEAVY SLEEP 2)
0
X
1
(Note 3-1) The Core regulator remains powered and the Ring oscillator is pow-
ered down during sleep cycles (SYSTEM HEAVY SLEEP 3)
1
X
1
(Note 3-1) The Core regulator is put into standby state and the Ring oscillator is
powered down during sleep cycles. (SYSTEM DEEPEST SLEEP)
Note 3-1
The latency following a wake event for the SMBus and UART is 600us (typ). It is less than 10us for
LPC, eSPI and PS2.
3.9.6 PROCESSOR CLOCK CONTROL REGISTER (PROC_CLK_CNTRL)
Offset ^20h
Bits
Description
31:8 RESERVED
7:0 Processor Clock Divide Value
1: divide 48 MHz Ring Oscillator by 1 (i.e., 48 MHz).
4: divide 48 MHz Ring Oscillator by 4 (i.e., 12 MHz).
16: divide 48 MHz Ring Oscillator by 16 (i.e., 3 MHz).
48: divide 48 MHz Ring Oscillator by 48 (i.e., 1 MHz).
No other values are supported.
3.9.7 EC SLEEP ENABLE 2 REGISTER (EC_SLP_EN2)
Type
RES
R/W
Default
Reset
Event
4h
nSYSR
ST
Offset ^24h
Bits
Description
31:24 RESERVED
23 Reserved - Should be set to ‘1’
Type
RES
R/W
Default
Reset
Event
0h
nSYSR
ST
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