MEC1404 Datasheet, PDF(247/572 Page) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

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MEC1404 Datasheet, PDF (247/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

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MEC140X/1X

Event

Sleep Button

Event Bit

SLPBTN_STS

RTC Alarm RTC_STS

Definition

The sleep button that has a status and an enable bit in the Runtime Regis-

ters to provide an SCI power management event on a button press. The

status bit is software Read/Writable by the EC; the enable bit is Read-only

by the EC.

The SLPBTN_STS bit is set by the Host to enable the generation of an

SCI due to the sleep button event. The status bit is set by the EC when it

generates a sleep button event and is cleared by the Host writing a â1â to

this bit (writing a â0â has no effect); it can also be cleared by the EC. If the

enable bit is set, the EC will generate an SCI power management event.

The ACPI specification requires that the RTC alarm generate a hardware

wake-up event from the sleeping state. The RTC alarm can be enabled as

an SCI event and its status can be determined through bits in the Runtime

Registers. The status bit is software Read/Writable by the EC; the enable

bit is Read-only by the EC.

The RTC_STS bit is set by the Host to enable the generation of an SCI

due to the RTC alarm event. The status bit is set by the EC when the RTC

generates an alarm event and is cleared by the Host writing a â1â to this bit

(writing a â0â has no effect); it can also be cleared by the EC. If the enable

bit is set, the EC will generate an SCI power management event.

FIGURE 15-2: describes the relationship of PM1 Status and Enable bits to the EC_SCI# pin.

FIGURE 15-2:

EC_SCI# INTERFACE

PM1_STS 2 PM1_EN 2

Register

Register

PWRBTN_STS

SLPBTN_STS

RTC_STS

EC_PM_STS Register

EC_SCI_STS

EC_SCI#

15.11 Runtime Registers

The registers listed in the Runtime Register Summary table are for a single instance of the ACPI PM1 interface. The

addresses of each register listed in this table are defined as a relative offset to the host âBase Addressâ defined in the

Runtime Register Base Address Table.

ï£ 2015 - 2016 Microchip Technology Inc.

DS00001956D-page 247

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