MEC1404 Datasheet, PDF (453/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
The following figures illustrate the VBAT-Power Control Interface logic:
FIGURE 37-2:
VBAT-POWERED CONTROL INTERFACE BLOCK DIAGRAM
VCI_IN0# Logic
VCI_IN1# Logic
VCI_OVRD_IN
POWER_UP_EVENT
0
VCI_FW_CONTRL
1
VCI_OUT
FW_EXT
VTRGD
The VCI_INx# Logic in the block diagram is illustrated in the following figure:
FIGURE 37-3:
VBAT-POWERED CONTROL INTERFACE BLOCK DIAGRAM
VCI_BUFFER_EN
IE
FILTER_BYPASS
VCI_IN_
POL
PIN
ENB
Filter
?
?
VCI_IN
POS
VCI_IN
NEG
RQ
S
LS
0
ENB
1
LE
VCI_IN#
37.8.1 INPUT POLARITY
The VCI_IN# pins have an optional polarity inversion. The inversion takes place after any input filtering and before the
VCI_IN signals are latched in the VCI_IN# status bits in the VCI Register. Edge detection occurs before the polarity
inversion. The inversion is controlled by battery-backed configuration bits in the VCI Polarity Register.
37.8.2 EDGE EVENT STATUS
Each VCI_IN# input pin is associated with two register bits used to record edge transitions on the pins. The edge detec-
tion takes place after any input filtering, before polarity control and occurs even if the VCI_IN# input is not enabled as
part of the VCI_OUT logic (the corresponding control bit in the VCI Input Enable Register is ‘0’) or if the state of the
VCI_IN# input is not latched (the corresponding control bit in the Latch Enable Register is ‘0’). One bit is set whenever
there is a high-to-low transition on the VCI_IN# pin (the VCI Negedge Detect Register) and the other bit is set whenever
there is a low-to-high transition on the VCI_IN# pin (the VCI Posedge Detect Register).
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DS00001956D-page 453