MEC1404 Datasheet, PDF (260/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
FIGURE 16-4:
GATEA20 IMPLEMENTATION DIAGRAM
nIOW
24MHz
Data
Address
IOW#
SAEN
64&AEN#
SD[7:0] = D1
SD[7:0] = FF
SD[7:0] = FE
D Q ^SET
Q CLR
D Q ^SET
Q CLR
nIOW
KRESET Gen
nIOW
Q ^SET
D Q CLR
IBF
AEN#&60
IOW#
AEN#&64
IOW#
VCC
AEN#&60
D Q ^SET
Q CLR
D Q ^SET
Q CLR
SETGA20L Reg (Any WR)
VCC
D Q ^SET
Q CLR
RSTGA20L Reg (Any WR)
CPU RESET
ENAB P92
Port 92 Reg (D1)
GATEA20 Reg WR (D0)
GATEA20
GATEA20 Reg RD (D0)
16.11.2 CPU_RESET HARDWARE SPEED-UP
The ALT_CPU_RESET bit generates, under program control, the ALT_RST# signal, which provides an alternate, means
to drive the MEC140X/1X CPU_RESET pin which in turn is used to reset the Host CPU. The ALT_RST# signal is inter-
nally NANDed together with the KBDRESET# pulse from the KRESET Speed up logic to provide an alternate software
means of resetting the host CPU.
Before another ALT_RST# pulse can be generated, ALT_CPU_RESET must be cleared to ‘0’ either by an nSIO_RESET
or by a write to the Port 92 Register with bit 0 = ‘0’. An ALT_RST# pulse is not generated in the event that the
ALT_CPU_RESET bit is cleared and set before the prior ALT_RESET# pulse has completed.
If the 8042EM Sleep Enable is asserted, or the 8042 EM ACTIVATE bit is de-asserted, the 1MHz clocks source is dis-
abled.
DS00001956D-page 260
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