MEC1404 Datasheet, PDF (178/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
FIGURE 10-4:
FULLY AGGREGATED PRIORITY ENCODER AND VECTOR ADDRESS
GIRQ8 Result
GIRQ8 ‐Bit[0]
Priority[1:0]
Vector Select
GIRQ8 Result
Priority
GIRQ(n‐1) Result
GIRQ(n‐1) ‐Bit[0]
Priority[1:0]
GIRQ(n‐1) Result
Priority
GIRQn Result
GIRQn ‐Bit[0]
Priority[1:0]
GIRQn Result
Priority
Vector_Address
GIRQ[n:8] Aggregated Vector Address
STEPS TO SET UP A PARTICULAR GIRQ GROUPING OF INTERRUPTS TO VECTOR TO AN ISR IN
AGGREGATED MODE.
1. Determine location in code space of the ISR to handle GIRQ “n”. Program this 17-bit offset into the GIRQ aggre-
gator control/vector address register. Of course, have the processor’s EBASE register programmed to the correct
location as well.
2. (optional) Clear all source bits for the interrupts within GIRQ “n”.
3. Enable the individual interrupts within GIRQ “n” that you wish the ISR to handle.
4. Enable global interrupts in the processor.
ILLUSTRATIVE SCENARIO.
GIRQ #8 has 31 GPIOs from pins configured to generate interrupts that will be handled by an ISR labeled
“GIRQ08_handler”. The 31 GPIOs are named (from GIRQ #8’s bit 0 through bit 30): GPIO001, GPIO002,….,GPIO030.
EBASE is at 0xbfd0_0000. The linker placed the handler at 0xbfd0_0500.
The firmware programs GIRQ #8’s aggregator control to 0x0000_0500, sets each interrupt source priority to, say, 0x0
(2 bits of priority), which corresponds to priority level 1 to the processor. Then enables all interrupt lines by writing
0xffff_ffff to GIRQ #8’s interrupt “enable set” register address.
If GPIO029 later fires an interrupt to the controller, the controller will send an EIC vector of 0x500 with a requested inter-
rupt priority level 1 to the processor. The same goes for any of the other GPIOs firing an interrupt via GIRQ #8.
DS00001956D-page 178
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