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| MEC1404 Datasheet, PDF (525/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC | |||
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43.19 PECI Interface
MEC140X/1X
Name
Description
MIN
MAX
Units
Notes
tBIT
tBIT,jitter
tBIT,drift
tH1
tH0
tPECIR
tPECIF
Bit time (overall time evident on PECI pin)
Bit time driven by an originator
Bit time jitter between adjacent bits in a PECI
message header or data bytes after timing has
been negotiated
Change in bit time across a PECI address or
PECI message bits as driven by the originator.
This limit only applies across tBIT-A bit drift and
tBIT-M drift.
High level time for logic 1
High level time for logic 0
Rise time
(measured from VOL to VIH,min , Vtt(nom)ï5%)
Fall time
(measured from VOH to VIL,max , Vtt(nom)+5%)
0.495
500
µsec
43-16
0.495
250
µsec
-
-
%
-
-
%
0.6
0.8
tBIT
0.2
0.4
tBIT
-
30 +
ns
(5 x #nodes)
-
(30 x #nodes)
ns
43-17
43-18
43-18
Note 43-16
Note 43-17
Note 43-18
The originator must drive a more restrictive time to allow for quantized sampling errors by a client
yet still attain the minimum time less than 500 µsec. tBIT limits apply equally to tBIT-A and tBIT-M . The
MEC140X/1X is designed to support 2 MHz, or a 500ns bit time. See the PECI 3.0 specification from
Intel Corp. for further details.
The minimum and maximum bit times are relative to tBIT defined in the Timing Negotiation pulse. See
the PECI 3.0 specification from Intel Corp. for further details.
â#nodesâ is the number of nodes on the PECI bus; host and client nodes are counted as one each.
Extended trace lengths may appear as extra nodes. Refer also to Table 25-2, "PECI Routing
Guidelines". See the PECI 3.0 specification from Intel Corp. for further details.
ï£ 2015 - 2016 Microchip Technology Inc.
DS00001956D-page 525
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