MEC1404 Datasheet, PDF (177/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
TABLE 10-2: INTERRUPT SOURCE, ENABLE SET, ENABLE CLEAR, AND RESULT BIT
ASSIGNMENTS (CONTINUED)
Aggreg Aggrega
ator IRQ tor Bit
HWB Instance Name
Interrupt Event
Wake
Event
Source Description
GIRQ26
0
GIRQ26
1
GIRQ26
2
GIRQ26
3
GIRQ26
4
GIRQ26
5
GIRQ26
6
GIRQ26
7
GIRQ26
8
GIRQ26
9
GIRQ26 10
GIRQ26
11
eSPI_Slave
eSPI_Slave
eSPI_Slave
eSPI_Slave
eSPI_Slave
eSPI_Slave
eSPI_Slave
eSPI_Slave
eSPI_Slave
eSPI_Slave
eSPI_Slave
eSPI_Slave
MSVW07_SRC0
MSVW07_SRC1
MSVW07_SRC2
MSVW07_SRC3
MSVW08_SRC0
MSVW08_SRC1
MSVW08_SRC2
MSVW08_SRC3
MSVW09_SRC0
MSVW09_SRC1
MSVW09_SRC2
MSVW09_SRC3
Yes Master-to-Slave Virtual Wire
Interrupt Event
Yes Master-to-Slave Virtual Wire
Interrupt Event
Yes Master-to-Slave Virtual Wire
Interrupt Event
Yes Master-to-Slave Virtual Wire
Interrupt Event
Yes Master-to-Slave Virtual Wire
Interrupt Event
Yes Master-to-Slave Virtual Wire
Interrupt Event
Yes Master-to-Slave Virtual Wire
Interrupt Event
Yes Master-to-Slave Virtual Wire
Interrupt Event
Yes Master-to-Slave Virtual Wire
Interrupt Event
Yes Master-to-Slave Virtual Wire
Interrupt Event
Yes Master-to-Slave Virtual Wire
Interrupt Event
Yes Master-to-Slave Virtual Wire
Interrupt Event
10.11.5 PRIORITY ENCODER AND DECODER
Every GIRQ Result bit has an associated Interrupt Priority Level (IPL) that is configurable by firmware (see Interrupt
Priority Control Registers on page 191). The Priority Encoder and Decoder logic always presents the interrupt event that
results in the highest Requested Interrupt Priority Level (RIPL) for a given mode of operation. The processor compares
the RIPL to the current IPL being serviced to determine if it should preempt the current IRQ handler or allow the current
IRQ handler to complete execution.
There are two modes of operation that effect how the hardware determines the RIPL: Aggregated Mode and Disaggre-
gated mode. Firmware can select the mode of operation per GIRQ by programming the JTEnable (Jump-Table Enable)
bit located in the Aggregator Control Registers. This allows the firmware to implement a fully aggregated solution, a fully
disaggregated solution, or a hybrid solution.
10.11.5.1 Fully Aggregated Mode
DETERMINING PRIORITY IN AGGREGATED MODE
In the fully aggregated mode, each GIRQ group is assigned the priority-level that is programmed for Result Bit 0 of that
group. Priority Control bits for GIRQ Result Bits [31:1] have no function in this mode.
The Priority Encoder and Decision Logic generates the Vector for the active GIRQ interrupt with the highest priority. A
GIRQ interrupt will be active if one or more of the bits within the GIRQ Result register are asserted. If two or more GIRQ
events are active with the same priority-level the lowest numbered GIRQ wins.
The following diagram illustrates this selection process.
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DS00001956D-page 177