MEC1404 Datasheet, PDF (428/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
TABLE 32-2: EC-ONLY REGISTER BASE ADDRESS TABLE
Block Instance
TFDP Debug Port
Instance
Number
0
Host
EC
Address Space
32-bit internal
address space
Base Address
0000_8C00h
The Base Address indicates where the first register can be accessed in a particular address space for a block instance.
TABLE 32-3: EC-ONLY REGISTER SUMMARY
Offset
00h
04h
Register Name (Mnemonic)
Debug Data Register
Debug Control Register
32.11.1 DEBUG DATA REGISTER
The Debut Data Register is Read/Write. It always returns the last data written by the TFDP or the power-on default ‘00h’.
Offset ^00h
Bits
Description
7:0 DATA
Debug data to be shifted out on the TFDP Debug port. While data
is being shifted out, the Host Interface will ‘hold-off’ additional
writes to the data register until the transfer is complete.
32.11.2 DEBUG CONTROL REGISTER
Type
R/W
Default
00h
Reset
Event
nSYSR
ST
Offset ^04h
Bits
Description
Type
7 Reserved
R
6:4 IP_DELAY
R/W
Inter-packet Delay. The delay is in terms of TFDP Debug output
clocks. A value of 0 provides a 1 clock inter-packet period, while a
value of 7 provides 8 clocks between packets:
3:2 DIVSEL
R/W
Clock Divider Select. The TFDP Debug output clock is determined
by this field, according to Table 32-4, "TFDP Debug Clocking":
Default
-
000b
Reset
Event
-
nSYSR
ST
00b
nSYSR
ST
DS00001956D-page 428
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