MEC1404 Datasheet, PDF (365/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
Note: Routing guidelines for the PECI_DAT pin is provided in Intel Platform design guides. Refer to the appropri-
ate Intel document for current information. See TABLE 25-2:.
TABLE 25-2: PECI ROUTING GUIDELINES
Trace Impedance
Spacing
Routing Layer
Trace Width
Length
50 Ohms +/- 15%
10 mils
Microstrip
Calculate to match impedance
1” - 15”
25.6 Host Interface
The registers defined for the PECI Interface are accessible by the various hosts as indicated in Section 25.11, "PECI
Interface Registers".
25.7 Power, Clocks and Reset
This section defines the Power, Clock, and Reset parameters of the block.
25.7.1 POWER DOMAINS
VTR
25.7.2
Name
CLOCK INPUTS
Description
The PECI Interface logic and registers are powered by VTR.
Name
48 MHz Ring Oscillator
25.7.3 RESETS
PECI Module Input Clock
Description
Name
nSYSRST
PECI Core Reset Input
25.8 Interrupts
This section defines the Interrupt Sources generated from this block.
Description
Source
Description
PECIHOST
PECI Host
25.9 Low Power Modes
The PECI Interface may be put into a low power state by the chip’s Power, Clocks, and Reset (PCR) circuitry.
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DS00001956D-page 365