MEC1404 Datasheet, PDF(422/572 Page) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

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MEC1404 Datasheet, PDF (422/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

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MEC140X/1X

31.11.1 BC-LINK STATUS REGISTER

Offset 00h

Bits

Description

Type

31:4 Reserved

R

7 RESET

R/W

When this bit is â1âthe BC_Link Master Interface will be placed in

reset and be held in reset until this bit is cleared to â0â. Setting

RESET to â1â causes the BUSY bit to be set to â1â. The BUSY

remains set to â1â until the reset operation of the BC Interface is

completed, which takes approximately 48 BC clocks.

The de-assertion of the BUSY bit on reset will not generate an

interrupt, even if the BC_BUSY_CLR_INT_EN bit is â1â. The BUSY

bit must be polled in order to determine when the reset operation

has completed.

6 BC_ERR

This bit indicates that a BC Bus Error has occurred. If an error

occurs this bit is set by hardware when the BUSY bit is cleared.

This bit is cleared when written with a â1â. An interrupt is generated

If this bit is â1â and BC_ERR_INT_EN bit is â1â.

Errors that cause this interrupt are:

R/WC

â¢ Bad Data received by the BASE (CRC Error)

â¢ Time-out caused by the COMPANION not responding.

All COMPANION errors cause the COMPANION to abort the oper-

ation and the BASE to time-out.31.11.2

5 BC_ERR_INT_EN

R/W

This bit is an enable for generating an interrupt when the BC_ERR

bit is set by hardware. When this bit is â1â, the interrupt signal is

enabled. When this bit is â0â, the interrupt is disabled.

4 BC_BUSY_CLR_INT_EN

R/W

This bit is an enable for generating an interrupt when the BUSY bit

in this register is cleared by hardware. When this bit is set to â1â, the

interrupt signal is enabled. When the this bit is cleared to â0â, the

interrupt is disabled. When enabled, the interrupt occurs after a BC

Bus read or write.

3:1 Reserved

R

0 BUSY

R

This bit is asserted to â1â when the BC interface is transferring data

and on reset. Otherwise it is cleared to â0â. When this bit is cleared

by hardware, an interrupt is generated if the BC_BUSY_CL-

R_INT_EN bit is set to â1â.

Default

-

1h

Reset

Event

-

nSYSR

ST

0h

nSYSR

ST

0b

nSYSR

ST

0h

nSYSR

ST

-

-

1h

nSYSR

ST

DS00001956D-page 422

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